1. Field of the Invention
This invention relates to timing circuits, and more particularly, to delay locked loop (DLL) circuits.
2. Description of the Related Art
Delay locked loops (DLLs) are commonly used in computer systems and other electronic systems in order to ensure proper timing. A typical delay locked loop includes a phase detector, a counter, and a programmable delay line. The phase detector may be used to compare the phase between two input clock signals, wherein one of the clock signals may be a reference clock signal and the other may be a clock signal fed back from the DLL output. The phase detector may generate an UP or DOWN signals based on the phase relationship between the input clock signals, which may then be driven to a counter. The counter may then count up or down, thereby adjusting the delay of the programmable delay line until the two input clock signals are in phase.
Since a typical phase detector may compare only the phase difference between two input clock signals, it is possible for a DLL to have multiple lock points. Thus, it is possible for the DLL to lock at a point that is N times the input period of a reference clock signal, wherein N is an integer value greater than or equal to one. When the goal is to generate certain type of signals (such as quadrature signals, i.e. signals with a 90xc2x0 phase difference), locking at a value of N greater than one may be unsuitable. In such cases, the designer of the DLL circuit must ensure that the DLL locks at a value of N=1.
A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit may be configured to cause the counter to increment, regardless of the phase relationship between a reference clock signal and the output clock signal of the DLL circuit. More particularly, the counter control circuit may cause the counter to increment, even if the phase detector outputs initially indicate that the counter is to decrement. The counter may continue incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line, until the phase detector indicates increment, then subsequently indicates decrement. This may eventually result in a phase lock between the reference clock signal and the output clock signal at a minimum delay at which a phase lock may be achieved among possible delays at which a lock might be achievable. Then, the counter control circuit may cause the counter in increment or decrement from the indications provided by the phase detector. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter may then increment or decrement its count as necessary in order to maintain or re-acquire a lock.
In one embodiment, the DLL circuit includes a phase detector, a counter control circuit, a counter, and a programmable delay line. The phase detector may receive a reference clock signal, as well as an output clock signal from the programmable delay line. The phase detector may determine the phase relationship between the reference clock signal and the output clock signal. In response to determining the phase relationship, the phase detector may generate signals indicating whether the counter is to be incremented or decremented, as well as indicating whether the DLL circuit has obtained a lock. The phase detector may drive these signals to a counter control circuit. In response, the counter control circuit may be configured to generate signals which cause the counter to increment or decrement. The counter control circuit may be configured to cause the counter to increment upon initialization of the DLL circuit, wherein initialization includes setting the value of the counter output to zero. A re-initialization of the DLL circuit may occur responsive the counter control circuit receiving a reset signal.
The counter may increment or decrement depending upon the signals received from the counter control circuit. The output of the counter may be driven to the programmable delay line, where the value of the count may adjust the delay of the reference clock signal and thereby produce an output clock signal. The output clock signal may be fed back to the phase detector for a phase comparison with the reference clock signal.
By forcing the counter to increment upon initialization or reset of the DLL circuit, the DLL circuit may be able to obtain a phase lock at a minimum delay of the programmable delay line. The delay at which a phase lock occurs may be at the delay at which the output clock and reference clock frequencies match. In one embodiment, the DLL circuit is configured to obtain a phase lock at N=1, wherein N is an integer multiple of the clock period.